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INTEGRATED CIRCUITS
DATA SHEET
SAA4977H Besic
Preliminary specification File under Integrated Circuits, IC02 1998 Jul 23
Philips Semiconductors
Preliminary specification
Besic
CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Analog-to-digital conversion Digital processing at 1fH level Digital processing at 2fH level Digital-to-analog conversion Microprocessor Memory controller Line locked clock generation Clock and sync interfacing 4 : 1 : 1 I/O interfacing Test mode operation I2C-bus control registers LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
SAA4977H
1998 Jul 23
2
Philips Semiconductors
Preliminary specification
Besic
1 FEATURES
SAA4977H
* Internal prefilter * Clamp circuit * Analog AGC * Line locked PLL * Triple YUV 8-bit Analog-to-Digital Converter (ADC) * Horizontal compression * Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) * 4 : 1 : 1 digital I/O interface * Digital CTI (DCTI) * Digital luminance peaking * Triple 10-bit Digital-to-Analog Converter (DAC) * Memory controller * Embedded microprocessor * 16 kbyte ROM * 256 byte RAM * I2C-bus interface 3 QUICK REFERENCE DATA SYMBOL VDDA(1,2,3) VDDD(1,2,3) VDDA(4,5) VDDD(4,5,6) VDDIO IDDA(1,2,3) IDDD(1,2,3) IDDA(4,5) IDDD(4,5,6) IDDIO Ptot Tamb 4 PARAMETER analog supply voltage front-end digital supply voltage front-end analog supply voltage back-end digital supply voltage back-end I/O supply voltage back-end analog supply current front-end digital supply current front-end analog supply current back-end digital supply current back-end I/O supply current back-end total power dissipation operating ambient temperature MIN. 4.75 4.75 3.15 3.15 4.75 - - - - - - -20 TYP. 5.0 5.0 3.3 3.3 5.0 85 65 25 40 1 - - MAX. 5.25 5.25 3.45 3.45 5.25 100 80 35 55 10 1.3 +60 V V V V V mA mA mA mA mA W C UNIT 2 GENERAL DESCRIPTION The SAA4977H is a video processing IC providing analog YUV interfacing, video enhancing features, memory controlling and an embedded 80C51 microprocessor core. It is applicable especially for field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) in cooperation with a 2.9 Mbit field memory. It is designed for applications together with: SAA4955/56TJ, TMS4C2972/73 (serial field memories) SAA4990H (PROZONIC) SAA4991WP (MELZONIC). * Synchronous No parity Eight bit Reception and Transmission (SNERT) interface.
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm VERSION SOT318-2
SAA4977H
QFP80
1998 Jul 23
3
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1998 Jul 23
26 YIN CLAMP 28 UIN AGC ANALOG PREFILTER 8 BIT TRIPLE ADC UV CLAMP CORRECTION VARIABLE Y-DELAY DOWN SAMPLING 4:4:4 TO 4:1:1 30 VIN
5
Philips Semiconductors
Besic
BLOCK DIAGRAM
UVO7 to UVO4 YO7 to YO0 8 45 to 38 4 37 to 34
UVI7 to UVI4 YI7 to YI0 4 8
59 51 to 58 to 62 VARIABLE Y-DELAY
Y-PEAKING BLANKING
79 TRIPLE DAC
HORIZONTAL COMPRESSION REFORMATTER UP SAMPLING FORMATTER 4:1:1 TO 4:2:2 4:2:2 TO 4:4:4 DCTI UP SAMPLING
YOUT
76
UOUT
10 BIT SIDEPANELS 74 VOUT
SAA4977H
4
ROM CONTROL INTERFACE TEST CONTROL BLOCK ACQUISITION PLL MEMORY CONTROL (ACQUISITION) CONTROL INTERFACE MEMORY CONTROL (DISPLAY) 63, 64 66 2 TMS TRST SWC LLA HA SELCLK VA WE RSTW LLD RE IE2 BLND 71, 72 68 2 HRD RST RAM MICROPROCESSOR I/O SNERTPORT BUS I2CBUS 15 49 47 33 22 17 20 32 24 70 9 3 to 7 5 P1.5 to P1.1 12, 13, 10 3 SNDA, SNCL, SNRST 1, 2 2 SDA, SCL
MGM592
HDFL VDFL
Preliminary specification
SAA4977H
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Besic
6 6.1 PINNING INFORMATION Pinning
SAA4977H
69 VDDD4
75 VDDA4
80 VDDA5
77 VSSA5
73 VSSA4
78 VSSA6
SDA SCL P1.5
65 VSSIO 64 IE2 63 RE 62 UVI4 61 UVI5 60 UVI6 59 UVI7 58 YI0 57 YI1 56 YI2 55 YI3 54 YI4 53 YI5 52 YI6 51 YI7 50 VSSD3 49 TRST 48 VSSD2 47 SWC 46 VDDD3 45 YO7 44 YO6 43 YO5 42 YO4 41 YO3 YO2 40
MGM593
76 UOUT
74 VOUT
79 YOUT
1 2 3
P1.4 4 P1.3 P1.2 P1.1 VDDD5 RST 5 6 7 8 9
SNRST 10 VDDD6 11 SNDA 12
SAA4977H
SNCL 13 VSSD4 14 TMS 15 VSSD1 16 SELCLK 17 VDDD1 18 VDDD2 19 VA 20 VSSA1 21 HA 22 VDDA1 23 RSTW 24 VDDA2 25 YIN 26 VSSA2 27 UIN 28 VDDA3 29 VIN 30 VSSA3 31 WE 32 LLA 33 UVO4 34 UVO5 35 UVO6 36 UVO7 37 YO0 38 YO1 39
Fig.2 Pin configuration.
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66 BLND
72 VDFL
71 HDFL
handbook, full pagewidth
67 VDDIO
68 HRD
70 LLD
Philips Semiconductors
Preliminary specification
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6.2 Pin description QFP80 package SYMBOL SDA SCL P1.5 P1.4 P1.3 P1.2 P1.1 VDDD5 RST SNRST VDDD6 SNDA SNCL VSSD4 TMS VSSD1 SELCLK VDDD1 VDDD2 VA VSSA1 HA VDDA1 RSTW VDDA2 YIN VSSA2 UIN VDDA3 VIN VSSA3 WE LLA UVO4 UVO5 UVO6 UVO7 YO0 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 I2C-bus I2C-bus serial data (P1.7) serial clock (P1.6) DESCRIPTION
SAA4977H
Table 1
Port 1 data input/output signal 5 Port 1 data input/output signal 4 Port 1 data input/output signal 3 Port 1 data input/output signal 2 Port 1 data input/output signal 1 digital supply voltage 5 (3.3 V) microprocessor reset input SNERT restart (port 1.0) digital supply voltage 6 (3.3 V) SNERT data SNERT clock digital ground 4 test mode select digital ground 1 select acquisition clock input; internal PLL if HIGH, external clock if LOW digital supply voltage 1 (5 V) digital supply voltage 2 (5 V) vertical synchronization input, acquisition part analog ground 1 analog/digital horizontal reference input analog supply voltage 1 (5 V) reset write signal output, memory 1 analog supply voltage 2 (5 V) Y analog input analog ground 2 U analog input analog supply voltage 3 (5 V) V analog input analog ground 3 write enable signal output, memory 1 acquisition clock input V digital output bit 0 V digital output bit 1 U digital output bit 0 U digital output bit 1 Y digital output bit 0
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Preliminary specification
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SAA4977H
SYMBOL YO1 YO2 YO3 YO4 YO5 YO6 YO7 VDDD3 SWC VSSD2 TRST VSSD3 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 RE IE2 VSSIO BLND VDDIO HRD VDDD4 LLD HDFL VDFL VSSA4 VOUT VDDA4 UOUT VSSA5
PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Y digital output bit 1 Y digital output bit 2 Y digital output bit 3 Y digital output bit 4 Y digital output bit 5 Y digital output bit 6 Y digital output bit 7 (MSB) digital supply voltage 3 (5 V) serial write clock output digital ground 2 test reset, active LOW digital ground 3 Y digital input bit 7 (MSB) Y digital input bit 6 Y digital input bit 5 Y digital input bit 4 Y digital input bit 3 Y digital input bit 2 Y digital input bit 1 Y digital input bit 0 U digital input bit 1 U digital input bit 0 V digital input bit 1 V digital input bit 0
DESCRIPTION
read enable signal output, memory 1 input enable signal output, memory 2 I/O ground horizontal blanking signal output, display part I/O supply voltage (5 V) horizontal reference signal output, deflection part digital supply voltage 4 (3.3 V) display clock input horizontal synchronization signal output, deflection part vertical synchronization signal output, deflection part analog ground 4 V analog output analog supply voltage 4 (3.3 V) U analog output analog ground 5
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Philips Semiconductors
Preliminary specification
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SAA4977H
SYMBOL VSSA6 YOUT VDDA5 7 7.1 7.1.1
PIN 78 79 80 analog ground 6 Y analog output
DESCRIPTION
analog supply voltage 5 (3.3 V) 7.1.4 TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION
FUNCTIONAL DESCRIPTION Analog-to-digital conversion CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16 AND UV TO 0 (2'S COMPLEMENT)
Three identical ADCs are used to convert Y, U and V with 16 MHz data rate. A multi-step type ADC is applied here. 7.2 7.2.1 Digital processing at 1fH level OVERLOAD DETECTION
A clamp circuit is applied for each input channel, to map the colourless black level in each video line (on the sync back porch) to level 16 for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch on the clamp action. An operational transconductance amplifier like construction, which references to voltage reference points in the ladders of the ADCs, will provide a current on the input of the YUV signals, in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to 100 A. When the clamping action is off, the residual clamp current should be very low in order not to drift away within a video line. 7.1.2 GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL
The overload detection provides information to make efficient use of the AGC. The number of overflows per video field in the luminance channel is accumulated by a 14-bit counter. The 8 MSBs of this counter can be read out by the microprocessor respectively via the I2C-bus. Overflow levels can be programmed as 216, 224, 232 and 240. 7.2.2 DIGITAL CLAMP CORRECTION FOR UV
A variable amplifier is used to map the possible YUV input range to the ADC range. A rise of 6 dB up to a drop fall of 6 dB w.r.t. the nominal values can be achieved. The gain setting within this range is done digitally via control registers. For this purpose a gain setting DAC is incorporated. The smallest step in the gain setting should be hardly visible on the picture, which can be met with smallest steps of 0.4%/step. Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may be gain adjusted already, whereas luminance is to be adjusted by the SAA4977H AGC. On the other hand, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain. 7.1.3 ANALOG ANTI-ALIASING PREFILTERING
During 32 samples within the clamp position the clamp error is measured and accumulated to make a low-pass filtered value of the clamp error. Then a vertical recursive filter is used to further low-pass this error value. This value can be read by the microprocessor or directly be used to correct the clamp error. It is also possible to give a fixed correction value by the microprocessor. 7.2.3 4 : 4 : 4 TO 4 : 1 : 1 DOWN-SAMPLING AND UV
CORING
The U and V samples from the ADC are low-pass filtered, before being subsampled with a factor of 2. Coring is applied to the subsampled signal to obtain no gain for low amplitudes which is considered to be noise. Coring levels can be programmed as 0 (off), 12, 1 and 2 LSB. The U and V samples from the 4 : 2 : 2 data are low-pass filtered again, before being subsampled a second time with a factor of 2 and formatted to 4 : 1 : 1 format. 7.2.4 Y-DELAY
A third order linear phase filter is applied on each of the Y, U and V channels. It provides a notch on fCLK (16 MHz) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for -3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired.
The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. The other settings provide four samples less delay to three sample more delay in Y. 8
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Philips Semiconductors
Preliminary specification
Besic
7.2.5 HORIZONTAL COMPRESSION
SAA4977H
* The original signal band-passed with centre frequency of 2.38 MHz. The band-passed and high-passed signals are weighted with factors 0, 116, 216, 316, 416, 516, 616, and 816, resulting in a maximum gain difference of 2 dB at the centre frequencies. Coring is added to obtain no gain for low amplitudes in the high-pass and band-pass filtered signal, which is considered to be noise. Coring levels can be programmed as 0 (off), 8, 16, 24 to 120 LSB w.r.t. the (signed) 11-bit filtered signal. In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 14, 24, and 44. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 14, 24, and 44. 7.3.4 Y-DELAY
For displaying 4 : 3 sources on 16 : 9 screens a horizontal signal compression can be done by data interpolation. Therefore two horizontal compression factors of either 4 or 7 are possible. Via the I2C-bus the compression can 3 6 be switched on or off and the compression mode 16 : 9 or 14 : 9 can be selected. When the compression mode is active, a reduced number of the interpolated data is stored in the field memory. To achieve sufficiently high accuracy in interpolation Variable Phase Delay filters are used (VPD10 for luminance, a multiplexed VPD06 for UV). 7.3 7.3.1 Digital processing at 2fH level 4 : 1 : 1 TO 4 : 2 : 2 UP-CONVERSION
An up-converter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. 7.3.2 DCTI
The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. Via the I2C-bus it is possible to control: gain width (see Fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.3), limit for pixel shift range (see Fig.5), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component. 7.3.3 Y-PEAKING
The Y samples can be shifted onto 8 positions w.r.t. the UV samples. This shift is meant to account for a possible difference in delay previous to the SAA4977H. The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide one to seven samples less delay in Y. 7.3.5 SIDEPANELS AND BLANKING
Sidepanels are generated by switching Y and the 4 MSBs of U and V to certain programmable values. The start and stop values for the sidepanels w.r.t. the rising edge of the HRD signal are programmable in a resolution of 4 LLD clock cycles. In addition, a fine shift of 0 to 3 LLD clock cycles of both values can be achieved. Blanking is done by switching Y to value 64 at 10-bit word and UV to value 0 (in 2's complement). Blanking is controlled by a composite signal HVBDA, consisting of a horizontal part HBDA and a vertical part VBDA. Set and reset value of the horizontal control signal HBDA are programmable w.r.t. the rising edge of the HRD signal, set and reset value of the vertical control signal VBDA are programmable w.r.t. the rising edge of the VA signal. The range of the Y output signal can be selected between 9 and 10 bits. In the case of 9 bits for the nominal signal there is room left for undershoot and overshoot (adding up to a total of 10 bits). In the case of selecting all 10 bits of the luminance DAC for the nominal signal any under or overshoot will be clipped (see Fig.11).
A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. The filtering is an addition of: * The original signal * The original signal high-passed with maximum gain at frequency = 12fs (8 MHz) * The original signal band-passed with centre frequency = 14fs (4 MHz) 1998 Jul 23 9
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Preliminary specification
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SAA4977H
MGM689
handbook, halfpage
1
signal amplitude 0.8
(1)
(2)
0.6
0.4
0.2
0 0 0.05 0.1 0.15 0.2 f/fs 0.25
(1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0.
Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.
handbook, full pagewidth
MGM690
500 digital signal 400 amplitude 300
(4) (3) (1) (2)
200 100 0
(5)
samples -100 -200 -300 (1) input signal. (2) gain = 1. (3) gain = 3. (4) gain = 5. (5) gain = 7. -400 -500
Fig.4 DCTI with variation of gain setting (limit = 1).
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SAA4977H
handbook, full pagewidth
500 digital signal 400 amplitude 300 200 100 0
(4) (3) (2) (1)
MGM691
samples -100 -200 -300 -400 (1) (2) (3) (4) input signal. limit = 1. limit = 2. limit = 3. -500
Fig.5 DCTI with variation of limit setting (gain = 7).
handbook, halfpage
1.2
MGM692
signal amplitude
0.8
0.4
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
Fig.6 DCTI post-filter transfer function.
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Philips Semiconductors
Preliminary specification
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SAA4977H
handbook, full pagewidth
10
MGM594
signal amplitude (dB) 8
(7)
(6) (5)
6
(4)
(3)
4
(2)
2
(1)
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
(1) (2) (3) (4) (5) (6) (7)
= 116. = 216. = 316. = 416. = 516. = 616. = 816.
Fig.7 Transfer function of the peaking high-pass filter with variation of ( = 0; = 0).
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SAA4977H
handbook, full pagewidth
10
MGM595
signal amplitude (dB) 8
(7)
(6) (5)
6
(4)
(3)
4
(2)
2
(1)
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
(1) (2) (3) (4) (5) (6) (7)
= 116. = 216. = 316. = 416. = 516. = 616. = 816.
Fig.8 Transfer function of the peaking band-pass with variation of ( = 0; = 0).
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Philips Semiconductors
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SAA4977H
handbook, full pagewidth
10
MGM596
signal amplitude (dB) 8
(7)
(6)
6
(5) (4)
4
(3)
(2)
2
(1)
0 0 0.1 0.2 0.3 0.4 f/fs 0.5
(1) (2) (3) (4) (5) (6) (7)
= 116. = 216. = 316. = 416. = 516. = 616. = 816.
Fig.9 Transfer function of peaking low band-pass with variation of ( = 0; = 0).
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Preliminary specification
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7.4 Digital-to-analog conversion
SAA4977H
When reading from the bus, one byte is loaded by the microprocessor for the address, the received byte is the data from the addressed SNERT location. 7.5.3 I/O PORTS
Three identical 10-bit DACs are used to map the 4 : 4 : 4 data to analog levels. 7.5 Microprocessor
The SAA4977H contains an embedded 80C51 microprocessor core including a 256 byte RAM and 16 kbyte ROM. The microprocessor runs on a 16 MHz clock, generated by dividing the 32 MHz display clock by a factor of 2. For controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in, that can be addressed as internal AUX RAM via MOVX type of instructions. 7.5.1 I2C-BUS
A parallel 8-bit I/O port (P1) is available, where P1.0 is used as the SNERT reset signal (SNRST), P1.1 to P1.5 can be used for application specific control signals, and P1.6 and P1.7 are used as I2C-bus signals (SCL and SDA). 7.5.4 WATCHDOG TIMER
The I2C-bus interface in the SAA4977H is used in a slave receive and transmit mode for communication with a central system microprocessor. The standardized bus frequencies of both 100 kHz and 400 kHz can be dealt with. The I2C-bus slave address of the SAA4977H is 0110100 R/W. For a detailed description of the transmission protocol refer to brochure "The I2C-bus and how to use it" (order number 9398 393 40011) and to Application note "I2C-bus register specification of the SAA4977H" (AN98054). 7.5.2 SNERT-BUS
The microprocessor contains an internal Watchdog Timer, which can be activated by setting the bit 4 in SFR PCON. Only a synchronous reset will clear this bit. To prevent a system reset the Watchdog Timer must be reloaded in time. The Watchdog Timer is incremented every 0.75 ms. The time interval between the timer's reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.6 Memory controller
A SNERT interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as the SAA4990H or SAA4991WP. The SNERT interface replaces the standard UART interface. In contrast to the 80C51 UART interface there are additional special function registers and there is no byte separation time between address and data. The SNERT interface transforms the parallel data from the microprocessor into 1 Mbaud SNERT data. The SNERT-bus consists of three signals: SNCL used as the serial clock signal and is generated by the SNERT interface; SNDA used as the bidirectional data line, and SNRST used as the reset signal and is generated by the microprocessor to indicate the start of a transmission. The read or write operation must be set by the microprocessor. When writing to the bus, 2 bytes are loaded by the microprocessor: one for the address, the other for the data.
The memory controller provides all necessary acquisition clock related write signals (WE and RSTW) and display clock related read signals (RE and IE2) to control one or two-field memory concepts. Furthermore the drive signals (HDFL and VDFL) for the horizontal and vertical deflection power stages are generated. Also a horizontal blanking pulse BLND is generated which can be used for peripheral circuits as SAA4990H. The memory controller is connected to the microprocessor via the host interface. Start and stop values for all pulses, referring to the corresponding horizontal or vertical reference signal, are programmable under control of the internal software. To allow user access to these control signals via the I2C-bus a range of subaddresses is reserved; for a detailed description of this user interface refer to Application Note "I2C-bus register specification of the SAA4977H" (AN98054). 7.6.1 WE
The write enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position w.r.t the rising edge of the HA signal and the vertical position w.r.t the rising edge of the VA signal are programmable.
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7.6.2 RSTW 7.7.2
SAA4977H
PLL CLOCK GENERATOR RUNNING AT 32 MHZ (2048 CLOCK CYCLES PER LINE)
Reset write signal for field memory 1; this signal is derived from the positive edge of the VA input signal and has a pulse width of 64 s. 7.6.3 RE
The basic frequency of the clock generator is 32 MHz. The type of PLL is known as `Petra PLL'. This is a purely analog clock generator, with analog frequency control via a loop filter on the measured phase error. 7.7.3 DIVIDE-BY-2 FOR MASTER CLOCK 16 MHZ
The read enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. The horizontal position w.r.t the rising edge of the HA signal and the vertical position w.r.t the rising edge of the VA signal are programmable. 7.6.4 IE2
A simple clock divider is used to generate 16 MHz out of 32 MHz. The advantage of this construction is the inherent 50% duty cycle on the acquisition clock. 7.7.4 DIVIDE BY ANOTHER 1024 TO GENERATE LINE FREQUENT, CLOCK SYNCHRONOUS Href SIGNAL
Input enable signal for field memory 2, can be directly set or reset by the microprocessor. 7.6.5 HDFL
The video lines contain 1024 clock cycles of 16 MHz. Therefore, frequency division by 1024 creates a 50% duty cycle line frequent signal Href. 7.8 Clock and sync interfacing
Horizontal deflection signal for driving a deflection circuit; this signal has a cycle time of 32 s and a pulse width of 76 LLD clock cycles. 7.6.6 VDFL
Typically the circuit operates as a two clock system, i.e. LLA is supplied with a 16 MHz clock and LLD with a 32 MHz clock. The line locked display clock LLD must be provided by the application. Also a line frequent signal must be provided by the application at pin HA. A vertical 50 or 60 Hz synchronization signal has to be applied on pin VA. It is also possible to use an external line locked acquisition clock, which must be provided at pin LLA. This operation mode can be selected by the SELCLK pin. When using the external acquisition clock the HA signal must be synchronous to the acquisition clock. A display clock synchronous line frequent signal is put out at pin HRD providing a duty factor of 50%. The rising edge of HRD is also the reference for display related control signals as BLND, RE, HDAV and HBDA. The acquisition clock is buffered internally and put out as serial write clock (SWC) for supplying the field memory.
Vertical deflection signal for driving a deflection circuit; this signal has a cycle time of 10 ms; the start and stop value w.r.t the rising edge of the VA signal is programmable in steps of 16 s. 7.6.7 BLND
Horizontal blanking signal for peripheral circuits e.g. SAA4990H, start and stop values w.r.t. the rising edge of HRD are programmable. 7.7 7.7.1 Line locked clock generation PHASE COMPARISON OF HA RISING EDGE WITH GENERATED Href SIGNAL
The HA signal, which has a nominal period of 64 s, is used as a timing reference for the line locked acquisition clock system. This HA signal may vary in position from application to application, related to the active video part. The phase comparator measures the delay between the HA and the internally generated, clock synchronous Href signal.
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Preliminary specification
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7.9 4 : 1 : 1 I/O interfacing Digital input and output bus format 4 : 1 : 1 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 INPUT PIN YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4
SAA4977H
Table 2
OUTPUT PIN YO7 YO6 YO5 YO4 YO3 YO2 Y01 YO0 UVO7 UVO6 UVO5 UVO4
The first phase of the 4 : 1 : 1 YUV dataword is available on the output bus one SWC clock cycle after the rising edge of the WE signal. The start position, when the first phase of the 4 : 1 : 1 YUV data word is expected on the input bus, can be defined by the internal control signal HDAV. The luminance output signal is in 8-bit straight binary format, whereas U and V input signals are in 2's complement format. Also the luminance input signal is expected in 8-bit straight binary format, whereas U and V input signals are expected in 2's complement format. The U and V input signals are inverted if the corresponding control bit uv_inv is set via the I2C-bus. 7.10 Test mode operation
The SAA4977H provides a test mode function which should not be entered by the customer. If the TRST input is driven HIGH, different test modes can be selected by applying a HIGH to the TMS input for a defined number of LLD clock cycles. To exit the test mode TMS and TRST must be driven LOW.
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7.11 I2C-bus control registers BIT NAME DESCRIPTION
SAA4977H
ADDRESS
Subaddress 00H to 2FH: reserved; note 1 Subaddress 30H to 32H (AGC) 30H 31H 32H 0 to 7 0 to 7 0 1 2 3 4 to 7 AGC_Y AGC_UV AGC_Y AGC_UV standby_f aaf_bypass - AGC gain for Y channel (2's complement relative to 0 dB): upper 8 bits AGC gain for U and V channel (2's complement relative to 0 dB): upper 8 bits AGC gain for Y channel LSB AGC gain for UV channel LSB front-end in standby mode if HIGH bypass for prefilter if HIGH reserved
Subaddress 33H (UV clamp correction) 33H 0 and 1 UVclcor_mode 2 to 4 5 to 7 Uclcor_fval Vclcor_fval clamp correction mode = auto, fixed, keep, reserved fixed value for clamp correction U channel fixed value for clamp correction V channel coring level = 0, 0.5, 1 and 2 LSB reserved vertical filtering of measured clamp reserved variable Y-delay in LLA clock cycles: -4, -3, -2, -1, 0, 1, 2 and 3 overload threshold: (216, 224, 232, 240) fill memory with constant value if HIGH reserved
Subaddress 34H (UV coring) 34H 0 and 1 UVcoring 2 and 3 - 4 and 5 UVcl_tau 6 and 7 - Subaddress 35H (Y delay) 35H 0 to 2 5 ydelay_f fill_mem 3 and 4 overl_thr 6 and 7 - Subaddress 36H and 37H (DCTI) 36H 0 to 2 3 to 6 7 37H 2 3 4 5 dcti_gain dcti_threshold dcti_ddx_sel dcti_separate dcti_protection dcti_filteron dcti_superhill DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7 DCTI threshold: 0, 1 to 15 DCTI selection of first differentiating filter; see Fig.3 DCTI limit for pixel shift range: 0, 1, 2 and 3 DCTI separate processing of U and V signals; 0 = off, 1 = on DCTI over the hill protection; 0 = off, 1 = on DCTI post-filter; 0 = off, 1 = on DCTI super hill mode; 0 = off, 1 = on reserved peaking alpha: 116 (0, 1, 2, 3, 4, 5, 6, 8) peaking beta: 116 (0, 1, 2, 3, 4, 5, 6, 8) reserved
0 and 1 dcti_limit
6 and 7 - Subaddress 38H and 3AH (peaking) 38H 0 to 2 3 to 5 pk_alpha pk_beta
6 and 7 -
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SAA4977H
ADDRESS 39H
BIT 0 to 2
NAME pk_tau peaking tau:
1 16
DESCRIPTION (0, 1, 2, 3, 4, 5, 6, 8) peaking amplitude dependent attenuation: 14 (0, 1, 2, 4) peaking attenuation of undershoots: 14 (0, 1, 2, 4) reserved peaking coring threshold 0, 8, 16 to 120 LSB reserved
3 and 4 pk_delta 5 and 6 pk_neggain 7 3AH 0 to 3 4 to 7 - pk_corthr -
Subaddress 3BH and 3CH (sidepanels overlay) 3BH 3CH 0 to 3 4 to 7 0 to 7 overlay_u overlay_v overlay_y sidepanels overlay U (4 MSB) sidepanels overlay V (4 MSB) sidepanels overlay Y (8 MSB)
Subaddress 3DH to 3FH (sidepanel position) 3DH 3EH 3FH 0 to 7 0 to 7 2 sidepanel_start sidepanel start position (8 MSB) w.r.t. the rising edge of HRD signal sidepanel_stop sidepanel stop position (8 MSB) w.r.t. the rising edge of HRD signal fine delay of sidepanel signal in LLD clock cycles: 0, 1, 2 and 3 output range (output range = 0: 9 bit for the nominal output signal, black level: 288 and white level: 767; output range = 1: 10 bit for the nominal output signal, black level 64 and white level 1023) inverts UV input signals: 0 = no inversion, 1 = inversion variable Y-delay in LLD clock cycles: -7, -6, -5, -4, -3, -2, -1 and 0 reserved output_range
0 and 1 sidepanel_fdel
3 4 to 6 7 Note
uv_inv ydelay_out -
1. Detailed information about the software dependent I2C-bus registers can be found in Application Note "I2C-bus register specification of the SAA4977H" (AN98054). 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA(1,2,3) VDDD(1,2,3) VDDA(4,5) VDDD(4,5,6) VDDIO Vi Tstg Tamb 9 PARAMETER analog supply voltage front-end digital supply voltage front-end analog supply voltage back-end digital supply voltage back-end digital I/O supply voltage back-end input voltage for all I/O pins storage temperature operating ambient temperature MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -20 -20 MAX. +5.25 +5.25 +3.45 +3.45 +5.25 +5.25 +150 +60 V V V V V V C C UNIT
THERMAL CHARACTERISTICS SYMBOL PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 50 UNIT K/W
Rth(j-a)
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SAA4977H
10 CHARACTERISTICS VDDD(1,2,3) = 4.75 to 5.25 V; VDDA(1,2,3) = 4.75 to 5.25 V; VDDD(4,5,6) = 3.15 to 3.45 V; VDDA(4,5) = 3.15 to 3.45 V; Tamb = 0 to 60 C; unless otherwise specified. SYMBOL Supply VDDA(1,2,3) VDDD(1,2,3) IDDA(1,2,3) IDDD(1,2,3) VDDA(4,5) VDDD(4,5,6) VDDIO IDDA(4,5) IDDD(4,5,6) IDDIO Dissipation Ptot Vi(p-p) Ci ILI II AGC(max) GAGC(max) AGC(acc) GAGC(acc) Vi(p-p) total power dissipation - - 1.3 W analog supply voltage front-end digital supply voltage front-end analog supply current front-end digital supply current front-end analog supply voltage back-end digital supply voltage back-end I/O supply voltage back-end analog supply current back-end digital supply current back-end I/O supply current back-end 4.75 4.75 - - 3.15 3.15 4.75 - - - 5.0 5.0 85 65 3.3 3.3 5.0 25 40 1 5.25 5.25 100 80 3.45 3.45 5.25 35 55 10 V V mA mA V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Luminance input signal (Y clamp level digital 16) Y input level (peak-to-peak value) input capacitance input leakage current input current maximum AGC attenuation maximum AGC gain AGC attenuation accuracy digital AGC gain accuracy digital clamp not active during clamping AGC fixed at 0 dB; note 1 0.95 - - - 5.75 5.75 - - 1.00 7 - - 6 6 8 8 1.05 15 100 150 - - - - V pF nA A dB dB bits bits
Colour difference input signals (U and V clamp level digital 128) U input level (peak-to-peak value) V input level (peak-to-peak value) Ci ILI II AGC(max) GAGC(max) AGC(acc) GAGC(acc) input capacitance input leakage current input current maximum AGC attenuation maximum AGC gain AGC attenuation accuracy digital AGC gain accuracy digital clamp not active during clamping AGC fixed at 0 dB; note 1 AGC fixed at 0 dB; note 1 1.29 1.00 - - - 5.75 5.75 - - 1.34 1.05 - - - 6 6 8 8 1.39 1.10 15 100 150 - - - - V V pF nA A dB dB bits bits
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SAA4977H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. - - - - -50 1 - -
MAX.
UNIT
Analog input transfer function (sample rate 16 MHz/8 bits) fCLK INL DNL S/N HD Gdif SVR maximum sample clock integral non linearity differential non linearity signal-to-noise ratio harmonic distortion (2nd to 5th harmonic) differential gain supply voltage rejection ramp input signal ramp input signal nominal amplitude; 0 to 8 MHz 18 -1 -0.75 43 MHz LSB LSB dB dB % dB +1 +0.75 - -37 2 -
95% amplitude; - Y at 4.3 MHz; UV at 1 MHz fCLK = 4.4 MHz; ADC only; at nominal AGC setting note 2 - 34
Analog Y, U and V input filter (third order linear phase filter with notch at fCLK) f(-3dB) (0.5) sb fnotch td(g) td(g)(dif) 3 dB down frequency attenuation at
1 f 2 CLK
fCLK = 16 MHz
5.4 7 30 15.5
5.6 8 - 16 55 20
5.8 - - 16.5 65 30
MHz dB dB MHz ns ns
(8 MHz)
stop band attenuation notch frequency group delay differential group delay within 1 to 6 MHz fCLK = 4 MHz
- -
Luminance output signal (output_range = 0: Y black level digital 288, white level digital 767, output_range = 1: Y black level digital 64, white level digital 1023); see Fig.11 Vo(p-p) Ro RL CL SVR ct S/N Y output level (peak-to-peak value) output resistance resistive load capacitive load supply voltage rejection crosstalk attenuation between outputs signal-to-noise ratio note 2 0 to 10 MHz nominal amplitude; 0 to 10 MHz ZL = 2 k 1.28 - 1 - 34 40 46 1.34 50 2 - - - - 1.40 100 - 25 - - - V k pF dB dB dB
Colour difference output signals (U and V digital range 0 to 1023) Vo(p-p) U output level (peak-to-peak value) V output level (peak-to-peak value) Gm(U-V) Ro RL CL SVR gain matching U to V output resistance resistive load capacitive load supply voltage rejection note 2 ZL = 2 k ZL = 2 k 1.28 1.28 - - 1 - 34 1.34 1.34 1 50 2 - - 1.40 1.40 3 100 - 25 - V V % k pF dB
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SAA4977H
SYMBOL ct S/N
PARAMETER crosstalk attenuation between outputs signal-to-noise ratio
CONDITIONS 0 to 10 MHz nominal amplitude; 0 to 10 MHz
MIN. 40 46
TYP. - - - -
MAX.
UNIT dB dB
Output transfer function (sample rate 32 MHz/10 bits) INL DNL integral non linearity differential non linearity IOH = -2.0 mA IOL = 1.6 mA see Fig.10 see Fig.10 IOH = -2.0 mA IOL = 1.6 mA see Fig.10 IOH = -2.0 mA IOL = 1.6 mA IOH = -2.0 mA IOL = 1.6 mA see Fig.10 see Fig.10 IOH = -0.06 mA IOL = 1.6 mA -2 -1 - - - - - - - - - - - - - - - - - - - - - - - +2 +1 - 0.4 20 - - 0.4 12 - 0.4 - 0.4 20 - - 0.4 5.5 0.8 LSB LSB
Digital output signals: YO, UVO, WE and RSTW (CL = 15 pF); timing referred to SWC clock VOH VOL td(o) th(o) HIGH-level output voltage LOW-level output voltage output delay time output hold time 2.4 - - 4 V V ns ns
Digital output signal: SWC (CL = 15 pF); timing referred to LLA clock VOH VOL td(o) VOH VOL HIGH-level output voltage LOW-level output voltage output delay time 2.4 - 3 V V ns
Digital output signal: HRD HIGH-level output voltage LOW-level output voltage 2.4 - V V
Digital output signals: IE2, BLND, RE, HDFL and VDFL (CL = 15 pF); timing referred to LLD clock VOH VOL td(o) th(o) VOH VOL VIH VIL VIH VIL tsu(i) th(i) HIGH-level output voltage LOW-level output voltage output delay time output hold time 2.4 - - 4 V V ns ns
Digital input/output signals: P1.1 to P1.5 and SNRST HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage 2.4 0 2.0 0 V V V V
Digital input signals: YI and UVI; timing referred to LLD clock HIGH-level input voltage LOW-level input voltage input set-up time input hold time see Fig.10 see Fig.10 2.0 - 4 3 5.5 0.8 - - V V ns ns
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SAA4977H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital input signal: HA; timing referred to LLA clock (only when SELCLK = 0, HA used as digital horizontal reference) VIH VIL tsu(i) th(i) VIH VIL fLLA clk VIH VIL tr tf fLLD clk VIH VIL tr tf HIGH-level input voltage LOW-level input voltage input set-up time input hold time see Fig.10 see Fig.10 2.0 - 7 4 - - - - - - 5.5 0.8 - - V V ns ns
Digital input signals: TRST, TMS, RST and VA HIGH-level input voltage LOW-level input voltage 2.0 - 5.5 0.8 V V
Digital input clock signal: LLA sample clock frequency clock duty factor HIGH-level input voltage LOW-level input voltage clock rise time clock fall time see Fig.10 see Fig.10 14 40 2.4 - - - 16 50 - - - - 34 60 - 0.6 5 5 MHz % V V ns ns
Digital input clock signal: LLD sample clock frequency clock duty factor HIGH-level input voltage LOW-level input voltage clock rise time clock fall time see Fig.10 see Fig.10 30 40 2.4 - - - 32 50 - - - - 34 60 - 0.6 5 5 - 0.4 400 - - - - - - - - MHz % V V ns ns
I2C-bus signal: SDA and SCL; note 3 VIH VIL VOL fSCL tHD;STA tLOW tHIGH tSU;DAT tSU;DAT1 tSU;DAT2 tSU;STA tSU;STO HIGH-level input voltage LOW-level input voltage LOW-level output voltage SCL clock frequency hold time START condition SCL LOW time SCL HIGH time data set-up time data set-up time (before repeated START condition) data set-up time (before STOP condition) set-up time repeated START set-up time STOP condition IOL = 3.0 mA 0.7VDDIO - - - - 0.6 1.3 0.6 100 0.6 0.6 0.6 0.6 - - - - - - - - - - - V V kHz s s s ns s s s s 0.3VDDIO V
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SAA4977H
SYMBOL
PARAMETER
CONDITIONS IOH = -2.0 mA IOL = 1.6 mA
MIN.
TYP. - - - - - - 1 - -
MAX.
UNIT
SNERT-bus: SNDA and SNCL; note 4 VOH VOL VIH VIL tsu(i) th(i) tcycle th(o) Notes 1. With AGC at -3 dB, U full ADC range is obtained at Vi = 1.89 V; with AGC at +6 dB, U full ADC range is obtained at Vi = 0.67 V; with AGC at -3 dB, V full ADC range is obtained at Vi = 1.48 V; with AGC at +6 dB, V full ADC range is obtained at Vi = 0.52 V. 2. Supply voltage ripple rejection, measured over a frequency range from 20 Hz to 50 kHz. This includes 12fV, fV, 2fV, fH and 2fH which are major load frequencies: SVR is relative variation of the full scale analog input for a supply variation of 0.25 V. 3. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure "I2C-bus and how to use it" (order number 9398 393 40011). 4. More information about the SNERT-bus protocol can be found in Application Note "The SNERT-bus specification" (AN95127). HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage input set-up time input hold time SNCL cycle time output hold time 2.4 - 2.0 - 700 0 - 50 V V V V ns ns s ns 0.4 5.5 0.8 - - - -
handbook, full pagewidth
tr
tf 2.4 V
CLOCK
1.5 V 0.6 V th(i) tsu(i) 2.0 V
INPUT DATA 0.8 V td(o) th(o) 2.4 V OUTPUT DATA 0.4 V
MGM597
Fig.10 Timing diagram.
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SAA4977H
handbook, full pagewidth
INPUT 8 bit
output_range = 1 white 255 1023
OUTPUT 10 bit
output_range = 0 1023
767
1.00 V
1.34 V
288 256
black 16 0
64 0
0
MGM598
Fig.11 Luminance levels.
11 APPLICATION The SAA4977H supports two different up-converter concepts. The simple one is shown in Fig.12. In this application only one field memory SAA4955TJ is needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode). The concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the SAA4956TJ is used instead of the SAA4955TJ. The SAA4977H supports a dual-clock system. The acquisition clock is taken from the digital front-end. The display control is based on a clock generated by an external H-PLL. By this structure the stability of the display is enhanced compared to a one-clock system if an unstable source like a VCR is used as an input. The second system supported by the SAA4977H is shown in Fig.13. This concept needs two field memories (SAA4955TJ) and the signal processing IC MELZONIC (SAA4991WP). The SAA4991WP allows a vector based motion estimation and compensation for a display of 100 Hz pictures in high-end TV sets which is free of motion artefacts. It additionally provides a variable vertical zoom function, noise and cross colour reduction. Furthermore a multi-PIP feature is supported making use of the field memories.
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SAA4977H
handbook, full pagewidth
+5 V +3.3 V 8, 11, 69, 75, 80 17, 18, 19, 23, 25, 29, 46, 67 9 10 F
YIN UIN VIN +3.3 V 19, 22 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5 6 7 8 9 10 11 12 13 14 +5 V 20, 21, 23 15 16 17, 18 38 37 36 35
26 28 30
8.2 k
SWC RSTW WE
47 24 32 51 52 53 54 55 56 57 58 59 60 61 62
45 44 43 42 41 40 39
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 YOUT UOUT VOUT SDA SCL HDFL VDFL
SAA4955TJ(1)
34 33 32 31 30 29 28
SAA4977H
38 37 36 35 34 79 76 74 1 2
25 26 1, 2, 39, 40
27 24
RE
63
20 22 HRD 71 14 to 16, 21, 27, 31, 72 48 to 50, 3 to 7, 68 33, 65, 73, 10, 12, 70 77, 78 13, 64, 66 n.c. VA HA
DISPLAY PLL
SRC
MGM599
(1) Alternatively SAA4956TJ.
Fig.12 Application diagram 1.
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SAA4977H
handbook, full pagewidth YIN
UIN VIN SWC +3.3 V 19, 22 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5 6 7 8 9 +5 V 20, 21, 23 15 16 17, 18 38 37 36 35 41 40 38 37 36 35 34 33 32 31 30 29 RE1 28 RSTW WE +5 V 1, 4, 20, 42, 46, 65, 78 48 49 50 51 52 53 54 55 56 57 58 59 61 +3.3 V 19, 22 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 3 4 5 6 7 8 9 +5 V 20, 21, 23 15 16 17, 18 38 37 36 35 WE2 11 64 66 67 68 69 70 71 72 73 74 75 RE2 76 77 2, 3, 5, 6, 7, 22, 26, 27, 47, 60, 63, 79 to 84 62 25 24 23 21 19 18 17 16 15 14 13 12 45 8 to 10 n.c. D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DISPLAY PLL SRC n.c. HRD RE 26 28 30 47 24 32 51 52 53 54 55 56 57 58 59 60 61 62 63 79 76 44 SNDA SNCL 12 13 20 22 71 14 to 16, 21, 27, 31, 72 48 to 50, 68 33, 65, 73, 3 to 7, 70 77, 78 10, 64, 66 HDFL VDFL 74 1 2 YOUT UOUT VOUT SDA SCL 45 44 43 42 41 40 39 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 8, 11, 69, 75, 80 17, 18, 19, 23, 25, 29, 9 46, 67 +5 V +3.3 V 10 F
8.2 k
SAA4955TJ 34 FM1 33 10
11 12 13 14 32 31 30 29 28 25 26 1, 2, 39, 40 27 24
SAA4977H
38 37 36 35 34
SAA4991WP
43
SAA4955TJ 34 FM2 33 10
11 12 13 14 32 31 30 29 28 25 26 1, 2, 39, 40 27 24
MGM600
VA HA
Fig.13 Application diagram 2.
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12 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA4977H
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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13 SOLDERING 13.1 Introduction
SAA4977H
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 13.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 13.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
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14 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4977H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 15 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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NOTES
SAA4977H
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/01/pp32
Date of release: 1998 Jul 23
Document order number:
9397 750 03258

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